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ltc2634 2634fc block diagram features a p p lications description quad 12-/10-/8-bit rail-to-rail dacs with 10ppm/c reference the ltc ? 2634 is a family of quad 12-, 10- and 8-bit volt- age output dacs with an integrated, high accuracy, low drift 10ppm/c reference in 16-lead qfn and 10-lead msop packages. it has rail-to-rail output buffers and is guaranteed monotonic. the ltc2634-l has a full-scale output of 2.5v, and operates from a single 2.7v to 5.5v supply. the ltc2634-h has a full-scale output of 4.096v, and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full-scale output to the external reference voltage. these dacs communicate via an spi/microwire compat- ible 3-wire serial interface which operates at clock rates up to 50mhz. serial data output (sdo), a hardware clear ( clr ), and an asynchronous dac update ( ldac ) capability are available in the qfn package. the ltc2634 incorporates a power-on reset circuit. options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset to mid-scale in external reference mode after power-up. integral nonlinearity (ltc2634-lz12) n integrated precision reference 2.5v full-scale 10ppm/c (ltc2634-l) 4.096v full-scale 10ppm/c (ltc2634-h) n maximum inl error: 2.5 lsb (ltc2634-12) n low noise: 0.75mv p-p 0.1hz to 200khz n guaranteed monotonic over C40c to 125c temperature range n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2634-l) n ultralow crosstalk between dacs (2.4nv?s) n low power: 0.6ma at 3v n power-on reset to zero-scale/mid-scale n double buffered data latches n tiny 16-lead 3mm 3mm qfn and 10-lead msop packages n mobile communications n process control and industrial automation n automatic test equipment n portable equipment n automotive register register register register dac a v outa (reflo) cs/ld sck ( ) qfn package only (ldac) gnd v outb v ref dac d register register register register dac b dac c v ref v outd ref v cc v ref v outc switch internal reference 32-bit shift register decode control logic power-on reset sdi 2634 bd (sdo) (clr) code 0 inl (lsb) 0 1 4095 2634 ta01 ?1 ?2 1024 2048 3072 2 v cc = 3v internal ref l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 5859606, 6891433, 6937178, 7414561.
ltc2634 2634fc p in c on f iguration ab solute m aximum r atings supply voltage (v cc ) ................................... C0.3v to 6v cs /ld, sck, sdi, ldac , clr , sdo, reflo.. C0.3v to 6v v outa -v outd .................... C0.3v to min (v cc + 0.3v, 6v) ref .................................. C0.3v to min (v cc + 0.3v, 6v) operating temperature range l tc2634c ................................................ 0c to 70c l tc2634i.............................................. C40c to 85c l tc2634h (note 3) ............................ C40c to 125c (notes 1, 2) 16 15 14 13 5 6 7 8 top view 17 ud package 16-lead (3mm s 3mm) plastic qfn 9 10 11 12 4 3 2 1v outa v outb ldac cs/ld v outd v outc ref clr v cc dnc gnd reflo sck dnc sdo sdi t jmax = 125c, q ja = 68c/w exposed pad (pin 17) is gnd, must be soldered to pcb 1 2 3 4 5 v cc v outa v outb cs/ld sck 10 9 8 7 6 gnd v outd v outc ref sdi top view 11 mse package 10-lead plastic msop t jmax = 125c, q ja = 35c/w exposed pad (pin 11) is gnd, must be soldered to pcb maximum junction temperature........................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) msop ............................................................... 300c
ltc2634 2634fc o r d er i n f ormation ltc2634 c ud -l z 12 #tr pbf lead free designator pbf = lead free tape and reel tr = 2,500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit power-on reset mi = reset to mid-scale in internal reference mode mx = reset to mid-scale in external reference mode z = reset to zero-scale in internal reference mode full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type ud = 16-lead qfn mse = 10-lead msop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) h = automotive temperature range (C40c to 125c) product part number consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2634 2634fc p ro d uct s election g ui d e part number part marking* v fs with internal reference power-on reset to code power-on reference mode resolution v cc maximum inl qfn msop ltc2634-lmi12 ltc2634-lmi10 ltc2634-lmi8 ldqx ldrf ldrn ltdrv ltdsc ltdsk 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2634-lmx12 ltc2634-lmx10 ltc2634-lmx8 ldqw ldrd ldrm ltdrt ltdsb ltdsj 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2634-lz12 ltc2634-lz10 ltc2634-lz8 ldqv ldrc ldrk ltdrs ltdrz ltdsh 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2634-hmi12 ltc2634-hmi10 ltc2634-hmi8 ldrb ldrj ldrr ltdry ltdsg ltdsp 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2634-hmx12 ltc2634-hmx10 ltc2634-hmx8 ldqz ldrh ldrq ltdrx ltdsf ltdsn 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2634-hz12 ltc2634-hz10 ltc2634-hz8 ldqy ldrg ldrp ltdrw ltdsd ltdsm 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb *above options are available in a 16-lead qfn package (ltc2634-ud) or 10-lead msop package (ltc2634-mse).
ltc2634 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz12/-lz10/-lz8 (v fs = 2.5v) ltc2634-8 ltc2634-10 ltc2634-12 symbol parameter conditions min typ max min typ max min typ max units dc performance resolution l 8 10 12 bits monotonicity v cc = 3v, internal ref. (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 3v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coeffcient v cc = 3v, internal ref. 10 10 10 v/c ge gain error v cc = 3v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coeffcient v cc = 3v, internal ref. (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation internal ref., mid-scale v cc = 3v 10%, C5ma i out 5ma l 0.009 0.016 0.035 0.064 0.14 0.256 lsb/ma internal ref., mid-scale v cc = 5v 10%, C10ma i out 10ma l 0.009 0.016 0.035 0.064 0.14 0.256 lsb/ma r out dc output impedance internal ref., mid-scale v cc = 3v 10%, C5ma i out 5ma l 0.09 0.156 0.09 0.156 0.09 0.156 internal ref., mid-scale v cc = 5v 10%, C10ma i out 10ma l 0.09 0.156 0.09 0.156 0.09 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short-circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C27 48 C48 ma ma power supply v cc positive supply voltage for specifed performance l 2.7 5.5 v i cc supply current (note 7) v cc = 3v, v ref = 2.5v, external reference v cc = 3v, internal reference v cc = 5v v ref = 2.5v, external reference v cc = 5v, internal reference l l l l 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 ma ma ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 0.5 0.5 20 30 a a
ltc2634 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz12/-lz10/-lz8 (v fs = 2.5v) symbol parameter conditions min typ max units reference input v ref input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 14 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 1.24 1.25 1.26 v reference temperature coeffcient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short-circuit current v cc = 5.5v, ref shorted to gnd 2.5 ma digital i/o v ih digital input high voltage v cc = 3.6v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v l l 0.8 0.6 v v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 8) l 2.5 pf ac performance t s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.3 3.8 4.2 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 2.1 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switch 0 C fs 2.1 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 200 180 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 35 40 680 730 v p-p v p-p v p-p v p-p
ltc2634 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-lmi12/-lmi10/-lmi8/-lmx12/-lmx10/-lmx8/-lz12/-lz10/-lz8 (v fs = 2.5v) symbol parameter conditions min typ max units t 1 sdi valid to sck setup l 4 ns t 2 sdi valid to sck hold l 4 ns t 3 sck high time l 9 ns t 4 sck low time l 9 ns t 5 cs/ld pulse width l 10 ns t 6 lsb sck high to cs/ld high l 7 ns t 7 cs/ld low to sck high l 7 ns t 8 clr pulse width l 20 ns t 9 ldac pulse width l 15 ns t 10 cs/ld high to sck positive edge l 7 ns sck frequency 50% duty cycle l 50 mhz t 11 cs/ld high to ldac high or low transition l 200 ns t 12 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v v cc = 2.7v to 5.5v l l 20 45 ns ns
ltc2634 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-hmi12/-hmi10/-hmi8/-hmx12/-hmx10/-hmx8/-hz12/-hz10/-hz8 (v fs = 4.096v) ltc2634-8 ltc2634-10 ltc2634-12 symbol parameter conditions min typ max min typ max min typ max units dc performance resolution l 8 10 12 bits monotonicity v cc = 5v, internal ref. (note 4) l 8 10 12 bits dnl differential nonlinearity v cc = 5v, internal ref. (note 4) l 0.5 0.5 1 lsb inl integral nonlinearity v cc = 5v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 lsb zse zero-scale error v cc = 5v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coeffcient v cc = 5v, internal ref. 10 10 10 v/c ge gain error v cc = 5v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coeffcient v cc = 5v, internal ref. (note 10) c-grade i-grade h-grade 10 10 10 10 10 10 10 10 10 ppm/c ppm/c ppm/c load regulation v cc = 5v 10%, internal ref., mid-scale, C10ma i out 10ma l 0.006 0.01 0.022 0.04 0.09 0.16 lsb/ma r out dc output impedance v cc = 5v 10%, internal ref., mid-scale, C10ma i out 10ma l 0.09 0.156 0.09 0.156 0.09 0.156 symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 4.096 v v psr power supply rejection v cc = 5v 10% C80 db i sc short-circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero-scale; v out shorted to v cc full-scale; v out shorted to gnd l l 27 C27 48 C48 ma ma power supply v cc positive supply voltage for specifed performance l 4.5 5.5 v i cc supply current (note 7) v cc = 5v, v ref = 4.096v, external reference v cc = 5v, internal reference l l 0.6 0.7 0.8 0.9 ma ma i sd supply current in power-down mode (note 7) v cc = 5v, c-grade, i-grade v cc = 5v, h-grade l l 0.5 0.5 20 30 a a
ltc2634 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-hmi12/-hmi10/-hmi8/-hmx12/-hmx10/-hmx8/-hz12/-hz10/-hz8 (v fs = 4.096v) symbol parameter conditions min typ max units reference input v ref input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 14 pf i ref reference current, power-down mode dac powered down l 0.005 1.5 a reference output output voltage l 2.032 2.048 2.064 v reference temperature coeffcient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short-circuit current v cc = 5.5v, ref shorted to gnd 4 ma digital i/o v ih digital input high voltage l 2.4 v v il digital input low voltage l 0.8 v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 8) l 2.5 pf ac performance t s settling time v cc = 5v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.8 4.2 4.8 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 3.0 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switch 0 C fs 2.4 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 250 230 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 35 50 680 750 v p-p v p-p v p-p v p-p
ltc2634 0 2634fc e lectrical c haracteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specifed. ltc2634-hmi12/-hmi10/-hmi8/-hmx12/-hmx10/-hmx8/-hz12/-hz10/-hz8 (v fs = 4.096v) symbol parameter conditions min typ max units t 1 sdi valid to sck setup l 4 ns t 2 sdi valid to sck hold l 4 ns t 3 sck high time l 9 ns t 4 sck low time l 9 ns t 5 cs/ld pulse width l 10 ns t 6 lsb sck high to cs/ld high l 7 ns t 7 cs/ld low to sck high l 7 ns t 8 clr pulse width l 20 ns t 9 ldac pulse width l 15 ns t 10 cs/ld high to sck positive edge l 7 ns sck frequency 50% duty cycle l 50 mhz t 11 cs/ld high to ldac high or low transition l 200 ns t 12 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v l 20 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c. operating at temperatures above 90c and with v cc > 4v requires v cc slew rates to be no greater than 73mv/ms. note 4: linearity and monotonicity are defned from code k l to code 2 n C 1, where n is the resolution and k l is given by k l = 0.016 ? (2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is defned from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is defned from code 16 to code 4,095. note 5: inferred from measurement at code 16 (ltc2634-12), code 4 (ltc2634-10) or code 1 (ltc2634-8), and at full-scale. note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 7: digital inputs at 0v or v cc . note 8: guaranteed by design and not production tested. note 9: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd. note 10: temperature coeffcient is calculated by dividing the maximum change in output voltage by the specifed temperature range.
ltc2634 2634fc t ypical p er f ormance c haracteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling t a = 25c, unless otherwise noted. ltc2634-l12 (internal reference, v fs = 2.5v) code 0 inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 1024 3072 2634 g01 4095 2048 v cc = 3v code 0 dnl (lsb) 1.0 0.5 0 ?0.5 ?1.0 1024 3072 2634 g02 4095 2048 v cc = 3v temperature (c) ?50 inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 ?25 125100755025 2634 g03 150 0 v cc = 3v inl (pos) inl (neg) temperature (c) ?50 dnl (lsb) 1.0 0.5 0 ?0.5 ?1.0 ?25 125100755025 2634 g04 150 0 v cc = 3v dnl (pos) dnl (neg) temperature (c) ?50 v ref (v) 1.260 1.255 1.250 1.245 1.240 ?25 125100755025 2634 g05 150 0 v cc = 3v 2s/div cs/ld 5v/div v out 1lsb/div 2634 g06 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 3.1s 2s/div cs/ld 5v/div v out 1lsb/div 2634 g07 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 100pf average of 256 events 4.2s
ltc2634 2634fc t ypical p er f ormance c haracteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling t a = 25c, unless otherwise noted. ltc2634-h12 (internal reference, v fs = 4.096v) code 0 inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 1024 3072 2634 g08 4095 2048 v cc = 5v code 0 dnl (lsb) 1.0 0.5 0 ?0.5 ?1.0 1024 3072 2634 g09 4095 2048 v cc = 5v temperature (c) ?50 inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 ?25 125100755025 2634 g10 150 0 v cc = 5v inl (pos) inl (neg) temperature (c) ?50 dnl (lsb) 1.0 0.5 0 ?0.5 ?1.0 ?25 125100755025 2634 g11 150 0 v cc = 5v dnl (pos) dnl (neg) temperature (c) ?50 v ref (v) 2.068 2.058 2.048 2.038 2.028 ?25 125100755025 2634 g12 150 0 v cc = 5v 2s/div cs/ld 5v/div v out 1lsb/div 2634 g13 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 3.8s 2s/div cs/ld 5v/div v out 1lsb/div 2634 g14 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 100pf average of 256 events 4.8s
ltc2634 2634fc t ypical p er f ormance c haracteristics integral nonlinearity (inl) differential nonlinearity (dnl) ltc2634-10 integral nonlinearity (inl) differential nonlinearity (dnl) ltc2634-8 load regulation current limiting ltc2634 offset error vs temperature t a = 25c, unless otherwise noted code 0 inl (lsb) 1.0 0.5 0 ?0.5 ?1.0 256 768 2634 g15 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 1.0 0.5 0 ?0.5 ?1.0 256 768 2634 g16 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 inl (lsb) 0.50 0.25 0 ?0.25 ?0.50 64 192 2634 g17 255 128 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 0.50 0.25 0 ?0.25 ?0.50 64 192 2634 g18 255 128 v cc = 3v v fs = 2.5v internal ref i out (ma) ?30 $v out (mv) 10 8 6 4 2 ?6 ?4 ?2 0 ?8 ?10 ?20 20100 2634 g19 30 ?10 v cc = 5v (ltc2634-h) v cc = 5v (ltc2634-l) v cc = 3v (ltc2634-l) internal ref. code = mid-scale i out (ma) ?30 $v out (v) 0.20 0.15 0.10 0.05 ?0.15 ?0.01 ?0.05 0 ?0.20 ?20 20100 2634 g20 30 ?10 v cc = 5v (ltc2634-h) v cc = 5v (ltc2634-l) v cc = 3v (ltc2634-l) internal ref. code = mid-scale temperature (c) ?50 offset error (mv) 3 2 1 0 ?1 ?2 ?3 ?25 125100755025 2634 g21 150 0
ltc2634 2634fc t ypical p er f ormance c haracteristics large-signal response mid-scale glitch impulse power-on reset glitch headroom at rails vs output current exiting power-down to mid-scale power-on reset to mid-scale supply current vs logic voltage hardware clr hardware clr to mid-scale ltc2634 t a = 25c, unless otherwise noted 2s/div v out 0.5v/div 2634 g22 v fs = v cc = 5v 1/4 scale to 3/4 scale 2s/div v out 5mv/div cs/ld 5v/div 2634 g23 ltc2634-h12, v cc = 5v 3.0nv?s typ ltc2634-l12, v cc = 3v 2.1nv?s typ 200s/div v out 5mv/div v cc 2v/div 2636 g24 ltc2634-l zero scale i out (ma) 0 v out (v) 5.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 0 1 7 8 9 6543 2634 g25 10 2 5v sourcing 3v (ltc2634-l) sourcing 3v (ltc2634-l) sinking 5v sinking 5s/div v out 0.5v/div cs/ld 2v/div 2634 g26 ltc2634-h v cc = 5v internal ref dacs a-c in power-down mode 200s/div v cc 2v/div v out 0.5v/div 2634 g27 ltc2634-h ltc2634-l 1s/div clr 5v/div v out 1v/div 2634 g29 v cc = 5v v ref = 4.096v code = full-scale 1s/div v out 1v/div clr 5v/div 2634 g30 v cc = 5v v ref = 4.096v code = full-scale logic voltage (v) 0 i cc (ma) 1.0 1.2 1.4 4 2634 g28 0.8 0.6 0.4 1 2 3 5 v cc = 5v v cc = 3v (ltc2634-l) sweep sck, sdi, cs/ld between 0v and v cc
ltc2634 2634fc t ypical p er f ormance c haracteristics mulitplying bandwidth noise voltage vs frequency gain error vs reference input 0.1hz to 10hz voltage noise dac-to-dac crosstalk (dynamic) gain error vs temperature ltc2634 t a = 25c, unless otherwise noted frequency (hz) db 2636 g31 2 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 ?18 1k 100k 1m 10k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale frequency (hz) 100 noise voltage (nv/ hz) 500 400 300 200 100 0 1k 100k 2636 g32 1m 10k v cc = 5v code = mid-scale internal ref ltc2634-h ltc2634-l 1s/div 10v/div 2634 g34 v cc = 5v, v fs = 2.5v code = mid-scale internal ref 2s/div v out 1mv/div 1 dac switch 0-fs 2v/div cs/ld 5v/div 2634 g35 ltc2634-h12, v cc = 5v 2.4nv?s typ c ref = 0.1f temperature (c) ?50 gain error (%fsr) 1.0 0.5 0 ?0.5 ?1.0 ?25 125100755025 2634 g36 150 0 reference voltage (v) 1 gain error (%fsr) 1.0 0.8 0.6 0.4 ?0.6 ?0.8 ?0.4 ?0.2 0.2 0 ?1.0 1.5 54.54 2634 g33 5.5 2 2.5 3 3.5 v cc = 5.5v gain error of 4 channels
ltc2634 2634fc p in functions (qfn/msop) v outa to v outd (pins 1-2, 11-12/pins 2-3, 8-9): dac analog voltage outputs. ldac (pin 3, qfn only): asynchronous dac update pin. if cs /ld is high, a falling edge on ldac immediately updates the dac registers with the contents of the input registers (similar to a software update). if cs /ld is low when ldac goes low, the dac registers are updated after cs /ld returns high. a low on the ldac pin powers up the dacs. a software power-down command is ignored if ldac is low. cs /ld (pin 4/pin 4): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the 32-bit shift register. when cs /ld is taken high, sck is disabled and the specifed command (see t able 1) is executed. sck (pin 5/pin 5): serial interface clock input. cmos and ttl compatible. dnc (pins 6, 15, qfn only): do not connect these pins. sdo (pin 7, qfn only): serial interface data output. the serial output of the 32-bit shift register appears at the sdo pin. the data transferred to the device via the sdi pin is delayed 32 sck rising edges before being output at the next falling edge. this pin is used for daisy-chain opera- tion, it is always driven and never goes high impedance, even when cs /ld is high. see the daisy-chain operation section. sdi (pin 8/pin 6): serial interface data input. data on sdi is clocked into the dac on the rising edge of sck. the ltc2634 accepts input word lengths of either 24 or 32 bits. clr (pin 9, qfn only): asynchronous clear input. a logic low at this level-triggered input clears all registers and causes the dac voltage output to reset to zero (ltc2634-z) or mid-scale (ltc2634-mi/-mx). cmos and ttl compatible. ref (pin 10/pin 7): reference voltage input or output. when external reference mode is selected, ref is an input (1v v ref v cc ) where the voltage supplied sets the full-scale dac output voltage. when internal reference is selected, the 10ppm/c 1.25v (ltc2634-l) or 2.048v (ltc2634-h) internal reference (half full-scale) is available at ref. this output may be bypassed to gnd with up to 10f and must be buffered when driving external dc load current. reflo (pin 13, qfn only): reference low pin. the voltage at this pin sets the zero-scale voltage of all dacs. this pin must be tied to gnd. gnd (pin 14/pin 10): ground. v cc (pin 16/pin 1): supply voltage input. 2.7v v cc 5.5v (ltc2634-l) or 4.5v v cc 5.5v (ltc2634-h). bypass to gnd with a 0.1f capacitor. exposed pad (pin 17/pin 11): ground. must be soldered to pcb ground.
ltc2634 2634fc block diagram register register register register dac a v outa (reflo) cs/ld sck ( ) qfn package only (ldac) gnd v outb v ref dac d register register register register dac b dac c v ref v outd ref v cc v ref v outc switch internal reference 32-bit shift register decode control logic power-on reset sdi 2634 bd (sdo) (clr)
ltc2634 2634fc t iming diagrams sdi sdo cs/ld sck 2634 f01a t 2 t 12 t 10 t 5 t 7 t 6 t 1 ldac t 3 t 4 1 2 3 23 24 t 11 t 9 cs/ld 2634 f01b t 11 ldac figure 1a figure 1b
ltc2634 2634fc o peration the ltc2634 is a family of quad voltage output dacs in 16-lead qfn and 10-lead msop packages. each dac can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. eighteen combinations of accuracy (12-, 10- and 8-bit), power-on reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode), and full- scale voltage (2.5v or 4.096v) are available. the ltc2634 is controlled using a 3-wire spi/microwire compatible interface. power-on reset the ltc2634-hz/ltc2634-lz clear the output to zero-scale when power is frst applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2634 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 5mv above zero- scale during power on. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2634-hmi/ltc2634-hmx/ltc2634-lmi/ l tc2634 - lmx provide an alternative reset, setting the output to mid-scale when power is frst applied. the ltc2634-lmi and ltc2634-hmi power up in internal reference mode, with the output set to a mid-scale volt- age of 1.25v and 2.048v, respectively. the ltc2634-lmx and ltc2634-hmx power up in external reference mode, with the output set to mid-scale of the external reference. default reference mode selection is described in the refer- ence modes section. power supply sequencing the voltage at ref (pin 10, qfn/pin 7, msop) must be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn- on and turn-off sequences, when the voltage at v cc is in transition. transfer function the digital-to-analog transfer function is: v k v v v out ideal n ref reflo reflo ( ) ? = ? ? ? ? ? ? ( ) + 2 where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5v (ltc2634-lmi/ltc2634-lmx/ltc2634-lz) or 4.096v (ltc2634-hmi/ltc2634-hmx/ltc2634-hz) when in internal reference mode, and the voltage at ref when in external reference mode. the resulting dac output span is 0v to v ref , as it is necessary to tie reflo to gnd. serial interface the cs /ld input is level-triggered. when this input is taken low, it acts as a chip-select signal, enabling the sdi and sck buffers and the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded frst; then the 4-bit dac address, a3-a0; and fnally the 16-bit data word. the data word comprises the 12-, 10- or 8-bit input code, ordered msb to lsb, followed by 4, 6 or 8 dont-care bits (ltc2634-12/ltc2634-10/ltc2634-8 respectively; see figure 2). data can only be transferred to the device when the cs /ld signal is low, beginning on the frst rising edge of sck. sck may be high or low at the falling edge
ltc2634 0 2634fc o peration c3 command input word (ltc2634-12) address data (12 bits + 4 don?t care bits) c2 c1 c0 a3 a2 a1 a0 d9d10d11 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x msb lsb c3 command input word (ltc2634-10) address data (10 bits + 6 don?t care bits) c2 c1 c0 a3 a2 a1 a0 d7d8d9 d6 d5 d4 d3 d2 d1 d0 x x x x x x msb lsb c3 command input word (ltc2634-8) address data (8 bits + 8 don?t care bits) c2 c1 c0 a3 a2 a1 a0 d5d6d7 d4 d3 d2 d1 d0 x x x x x x x x msb lsb 2634 f02 table 1. command codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power up) dac register n 0 0 1 0 write to input register n, update (power up) all 0 0 1 1 write to and update (power up) dac register n 0 1 0 0 power-down dac n 0 1 0 1 power-down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down internal reference) 1 1 1 1 no operation *command codes not shown are reserved and should not be used. table 2. address codes address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs * address codes not shown are reserved and should not be used. figure 2. command and data input format of cs /ld. the rising edge of cs /ld ends the data transfer and causes the device to execute the command specifed in the 24-bit input sequence. the complete sequence is shown in figure 3a. the command (c3-c0) and address (a3-a0) assignments are shown in tables 1 and 2. the frst four commands in table 1 consist of write and update operation. a write operation loads a 16-bit data word from the 24-bit shift register into the input register of the selected dac, n. an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 12-, 10- or 8-bit input code, and is converted to an analog voltage at the dac output. write to and update combines the frst two commands. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram.
ltc2634 2634fc o peration while the minimum input sequence is 24 bits, it may optionally be extended to 32 bits to accommodate micro- processors that have a minimum word width of 16 bits (2 bytes). to use the 32-bit width, 8 dont care bits must be transferred to the device frst, followed by the 24-bit sequence described. figure 3b shows the 32 -bit sequence. the 16-bit data word is ignored for all commands that do not include a write operation. daisy-chain operation (qfn package) the serial output of the shift register appears at the sdo pin on the qfn package. data transferred to the device from the sdi input is delayed 32 sck rising edges before being output at the next sck falling edge, therefore, daisy chaining multiple ltc2634 dacs requires 32-bit data write cycles. the sdo output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., sck, sdi and cs /ld). such a daisy-chain series is confgured by connecting sdo of each upstream device to sdi of the next device in the chain. the shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the frst instruction addresses the last device in the chain and so forth. the sck and cs /ld signals are common to all devices in the series. figure 5 shows a block diagram for daisy-chain operation. in use, cs /ld is frst taken low. then the concatenated input data is transferred to the chain, using sdi of the frst device as the data input. when the data transfer is complete, cs /ld is taken high, completing the instruction sequence for all devices simultaneously. a single device can be controlled by using the no-operation command (1111) for the other devices in the chain. reference modes for applications where an accurate external reference is either not available, or not desirable due to limited space, the ltc2634 has a low noise, user-selectable, integrated reference. the integrated reference voltage is internally amplifed by 2x to provide the full-scale dac output volt- age range. the ltc2634-lmi/ltc2634-lmx/ltc2634-lz provides a full-scale dac output of 2.5v. the ltc2634- h m i/ltc2634 - hmx/ltc2634-hz provides a full-scale dac output of 4.096v. the internal reference can be useful in applications where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110b, and is the power-on default for ltc2634-hz/ltc2634-lz, as well as for ltc2634-hmi/ ltc2634-lmi. the 10ppm/c, 1.25v (ltc2634-lmi/ltc2634-lmx/ ltc2634-lz) or 2.048v (ltc2634-hmi/ltc2634-hmx/ ltc2634-hz) internal reference is available at the ref pin. adding bypass capacitance to the ref pin will improve noise performance; 0.1f is recommended, and up to 10f can be driven without oscillation. the ref output must be buffered when driving an external dc load current. alternatively, the dac can operate in external reference mode using command 0111b. in this mode, an input voltage supplied externally to the ref pin provides the reference (1v v ref v cc ) and the supply current is reduced. the external reference voltage supplied sets the full-scale dac output voltage. external reference mode is the power-on default for ltc2634-hmx/ltc2634-lmx. the reference mode of ltc2634-hz/ltc2634-lz/ l tc2634 - hmi/ltc2634-lmi (internal reference power-on default), can be changed by software command after power up. the same is true for ltc2634-hmx/-lmx (external reference power-on default). the ltc2634s qfn package offers a reflo pin for the negative reference. reflo must be connected to gnd.
ltc2634 2634fc o peration power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four dac outputs are needed. when in power down, the buffer amplifers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 200k resistors. input- and dac-register contents are not disturbed during power down. any dac channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, (n). the supply current is reduced approximately 20% for each dac powered down. the integrated reference is automatically powered down when external reference is selected using command 0111b. in addition, all the dac channels and the integrated reference together can be put into power- down mode using power-down chip command 0101b. when the integrated reference and all dac channels are in power-down mode, the ref pin becomes high imped- ance (typically > 1g). for all power-down commands the 16-bit data word is ignored. normal operation resumes after executing any command that includes a dac update, (as shown in table 1) or pull- ing the asynchronous ldac pin low. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than four dacs are in a powered-down state prior to the update command, the power-up delay time is 10s. however, if all four dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the dac amplifers and reference buffers. in this case, the power-up delay time is 12s. the power-up of the integrated reference depends on the command that powered it down. if the reference is powered down using the select external reference com- mand (0111b), then it can only be powered back up using select internal reference command (0110b). however, if the reference was powered down using power-down chip command (0101b), then in addition to select internal reference command (0110b), any command (in software or using the ldac pin) that powers up the dacs will also power up the integrated reference. voltage output the ltc2634s integrated rail-to-rail amplifer has guaran- teed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the amplifers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1ma, or 50mv). see the graph headroom at rails vs output current in the typical performance character- istics section. the amplifer is stable driving capacitive loads of up to 500pf.
ltc2634 2634fc o peration rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the dac cannot go below ground, it may limit for the lowest codes as shown in figure 4b. similarly, limiting can occur near full-scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 4c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defned and tested over the region of the dac transfer function where no output limiting can occur. board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2634 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2634 is no more susceptible to this effect than any other parts of this type; on the con- trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa- rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2634 is sinking large currents, this current fows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to confne digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap.
ltc2634 2634fc o peration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 cs/ld sck sdi command word address data word 24-bit input word 2634 f03a figure 3a. ltc2634-12 24-bit load sequence (minimum input word) ltc2634-10 sdi data word: 10-bit input code + 6 dont care bits ltc2634-8 sdi data word: 8-bit input code + 8 dont care bits figure 3b. ltc2634-12 32-bit load sequence (required for daisy-chain operation) ltc2634-10 sdi data word: 10-bit input code + 6 dont care bits ltc2634-8 sdi data word: 8-bit input code + 8 dont care bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3xxxxxxxx cs/ld sck sdi command word address word data word don?t care c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3xxxxxxxx sdo current 32-bit input word 2634 f03b previous 32-bit input word t 2 t 3 t 4 t 1 t 12 d11 17 sck sdi sdo previous d10 previous d11 18 d10
ltc2634 2634fc o peration 2634 f04 input code (4b) (4a) (4c) output voltage negative offset 0v 2,048 0 0v 4,095 input code output voltage v ref = v cc v ref = v cc input code output voltage positive fse figure 4. effects of rail-to-rail operation on a dac transfer curve (shown in 12 bits) (4a) overall transfer function (4b) effect of negative offset for codes near zero (4c) effect of postitive full-scale error for codes near full-scale sdi sdo ltc2634ud sck 5 6 7 6 7 6 7 data output 4 cs/ld sdi sdo sck 5 4 cs/ld sdi sdo 2634 f05 sck 5 4 cs/ld cs/ld sck sdi ltc2634ud ltc2634ud ? ? ? figure 5. daisy-chain operation (qfn only)
ltc2634 2634fc typical application ? + dac a dac d ltc2755 r com1 r in1 60 0.1f 0.1f 0.1f 2 3 4 5 6 outa 2 3 59 1 4 8 2 58 19 5 6 7 4 ?15v 15v 8 r ofsa r fba r vosa gnd i out1a i out2a v dd 15 5v 61 0.1f 0.1f outc ?15v 30k lt1634-1.25 outb 0.1f 64 63 62 r efa ? + 1/2 lt1469 1/2 lt1469 ? + ltc6240 15v ?15v dac c + ? + ? dac b ?15v 30k ?15v 30k serial bus dac a dac b cs/ld sck 10 2634 ta02 8 9 0.1f 1 gnd 7 ref ltc2634mse-lmi12 v cc sdi dac c dac d m9 m3 m1 out v out 5v lt1991 ref v ee v cc 8 9 10 p1 p3 p9 1 2 3 5v 0.1f 0.1f 4 7 5 6 15v ?15v lt1634-1.25 lt1634-1.25 ltc2634 dacs adjusts ltc2755-16 offsets, amplifed with lt ? 1991 pga to 5v
ltc2634 2634fc p ackage description ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom view?exposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 p0.05 0.50 bsc package outline
ltc2634 2634fc p ackage description mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev d) msop (mse) 0210 rev d 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 p 0.152 (.193 p .006) 0.497 p 0.076 (.0196 p .003) ref 8910 10 1 7 6 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0o ? 6o typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 1.68 p 0.102 (.066 p .004) 1.88 p 0.102 (.074 p .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 p 0.0508 (.004 p .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
ltc2634 2634fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number a 10/09 changes to electrical characteristics maximum limits 5, 6, 8, 9 b 12/09 change pin name to dnc 2, 16 c 06/10 revised note 3 in the electrical characteristics section added typical application and replaced related parts list 10 30
ltc2634 0 2634fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0610 rev c ? printed in usa r elate d p arts typical application ? + dac a dac d ltc2755 r com1 r in1 60 0.1f 0.1f 0.1f 2 3 4 5 6 outa 2 3 59 1 4 8 2 58 19 5 6 7 4 ?15v 15v 8 r ofsa r fba r vosa gnd i out1a i out2a v dd 15 5v 61 0.1f 0.1f outc ?15v 30k lt1634-1.25 outb 0.1f 64 63 62 r efa ? + 1/2 lt1469 1/2 lt1469 ? + ltc6240 15v ?15v dac c + ? + ? dac b ?15v 30k ?15v 30k serial bus dac a dac b cs/ld sck 10 2634 ta02 8 9 0.1f 1 gnd 7 ref ltc2634mse-lmi12 v cc sdi dac c dac d m9 m3 m1 out v out 5v lt1991 ref v ee v cc 8 9 10 p1 p3 p9 1 2 3 5v 0.1f 0.1f 4 7 5 6 15v ?15v lt1634-1.25 lt1634-1.25 ltc2634 dacs adjusts ltc2755-16 offsets, amplifed with lt1991 pga to 5v part number description comments ltc2654/ltc2655 quad 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c maximum reference 4lsb inl maximum at 16 bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit, spi v out dacs with external reference 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 16-lead ssop package ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2635 quad 12-/10-/8-bit i 2 c v out dacs with 10ppm/c reference 2.5lsb inl, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, 16-pin 3mm 3mm qfn and 10-lead msop packages ltc2656/ltc2657 octal 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c maximum reference 4lsb inl maximum at 16 bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 5mm qfn and 16-lead tssop packages ltc2636/ltc2637 octal 12-/10-/8-bit, spi/i 2 c v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 14-lead 4mm 3mm dfn and 16-lead msop packages ltc2630/ltc2631 single 12-/10-/8-bit, spi/ i 2 c v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to- rail output, sc70 (ltc2630)/thinsot ? (ltc2631) packages ltc2640 single 12-/10-/8-bit, spi v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, thinsot package ltc1664 quad 10-bit, serial v out dac v cc = 2.7v to 5.5v, micropower, rail-to-rail output in 16-pin narrow ssop amplifers lt1991 precision, 100a gain selectable amplifer gain accuracy of 0.04%, gains from C13 to 14, 100a precision op amp lt1469 dual 90mhz, 22v/s 16-bit accurate operational amplifer 90mhz gain bandwidth, 125v offset, 900ns, 22v/s slew rate precision op amp

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